US 11,928,060 B2
Transfer of cachelines in a processing system based on transfer costs
Sriram Srinivasan, Austin, TX (US); John Kelley, Fort Collins, CO (US); and Matthew Schoenwald, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Feb. 8, 2022, as Appl. No. 17/666,950.
Application 17/666,950 is a continuation of application No. 16/700,671, filed on Dec. 2, 2019, granted, now 11,275,688.
Prior Publication US 2022/0237120 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/084 (2016.01)
CPC G06F 12/084 (2013.01) [G06F 2212/1021 (2013.01); G06F 2212/1041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing system comprising:
a plurality of compute units, each compute unit having a private cache; and
a shared cache coupled to the plurality of compute units, wherein the shared cache is configured to:
transfer a valid copy of a requested cacheline from a private cache of a compute unit of the plurality of compute units having a lowest transfer cost to a private cache of a requesting compute unit of the plurality of compute units, the lowest transfer cost is identified based on each distance between the requesting compute unit and the private caches having a valid copy of the requested cacheline and based on each corresponding distance between the shared cache and the private caches having a valid copy of the requested cacheline.