US 11,928,059 B2
Host-managed coherent device memory
Mahesh S. Natu, Folsom, CA (US); and Vivekananthan Sanjeepan, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 15, 2022, as Appl. No. 17/721,403.
Application 17/721,403 is a continuation of application No. 16/023,984, filed on Jun. 29, 2018, granted, now 11,347,643.
Prior Publication US 2022/0237121 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0811 (2016.01); G06F 9/4401 (2018.01); G06F 9/46 (2006.01); G06F 12/0875 (2016.01); G06F 12/0893 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 9/4411 (2013.01); G06F 9/468 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor comprising control logic to:
determine that an endpoint device connected to the processor can implement one or more host-managed device memory (HDM) ranges via an accelerator link protocol;
map the one or more HDM ranges to a corresponding system address space, wherein each HDM range is exposed as a memory-only non-uniform memory access (NUMA) node; and
perform memory transactions with the one or more HDM ranges.