CPC G06F 12/0811 (2013.01) [G06F 9/4411 (2013.01); G06F 9/468 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01)] | 25 Claims |
1. An apparatus comprising:
a processor comprising control logic to:
determine that an endpoint device connected to the processor can implement one or more host-managed device memory (HDM) ranges via an accelerator link protocol;
map the one or more HDM ranges to a corresponding system address space, wherein each HDM range is exposed as a memory-only non-uniform memory access (NUMA) node; and
perform memory transactions with the one or more HDM ranges.
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