US 11,928,026 B2
Memory and operation method of memory
Munseon Jang, San Jose, CA (US); Hoi Ju Chung, San Jose, CA (US); and Jang Ryul Kim, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 27, 2023, as Appl. No. 18/174,648.
Application 18/174,648 is a continuation of application No. 17/329,681, filed on May 25, 2021, granted, now 11,698,835.
Claims priority of provisional application 63/080,850, filed on Sep. 21, 2020.
Claims priority of provisional application 63/042,230, filed on Jun. 22, 2020.
Prior Publication US 2023/0222033 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for operating a memory, comprising:
reading data and an error correction code from a memory core;
correcting an error of the read data based on the read error correction code to produce error-corrected data;
obtaining write data which is transferred from outside of the memory;
generating new data by replacing a portion of the error-corrected data with the write data, the portion becoming a write data portion;
generating a new error correction code based on the new data; and
writing the write data portion and the new error correction code into the memory core without writing a remaining portion of the error-corrected data into the memory core.