US 11,928,024 B1
Atomic correction of single bit errors within a memory
Karthik Thucanakkenpalayam Sundararajan, Fremont, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 26, 2022, as Appl. No. 17/896,971.
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1064 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method comprising:
detecting, by a processing device, a single bit error with a memory, wherein the memory is accessed via data cache stages of a pipeline, and comprises a plurality of addresses storing a plurality of values;
stopping, based on detecting the single bit error, the data cache stages of the pipeline from accepting new transactions;
selecting, based on stopping the new transactions from being accepted, each of the plurality of addresses to read a value associated with each of the plurality of addresses; and
correcting each single bit error detected within the plurality of values.