CPC G06F 11/1004 (2013.01) [G06F 11/0703 (2013.01); G06F 11/073 (2013.01); G06F 11/1679 (2013.01); H03M 13/09 (2013.01)] | 20 Claims |
1. A memory controller to control memory, the memory controller comprising:
circuitry to transmit, to the memory, a write command and an associated address;
circuitry to generate error detection information, dependent on the associated address;
circuitry to detect, using the error detection information and additional information received from the memory, whether the associated address as received by the memory contains an error; and
circuitry to transmit to the memory, after a delay time with respect to the write command, a second communication, wherein the second communication upon receipt by the memory will cause the memory to store write data associated with the write command into a storage array of the memory.
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