US 11,928,018 B2
Coordinated error protection
Scott E. Schaefer, Boise, ID (US); and Aaron P. Boehm, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2022, as Appl. No. 17/889,203.
Claims priority of provisional application 63/294,289, filed on Dec. 28, 2021.
Prior Publication US 2023/0205620 A1, Jun. 29, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/0793 (2013.01) [G06F 11/073 (2013.01); G06F 11/1048 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, from a memory device, a set of data and an indication of whether a first error management procedure performed by the memory device on the set of data detected one or more errors in the set of data;
performing, at a host device, a second error management procedure on the set of data received from the memory device;
generating, based at least in part on the indication and the second error management procedure, a plurality of bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both; and
validating or discarding the set of data based at least in part on the plurality of bits.