CPC G06F 1/10 (2013.01) [G06F 1/08 (2013.01); H03K 19/20 (2013.01); H03K 3/037 (2013.01)] | 22 Claims |
1. An apparatus comprising:
an OR-AND-INVERT gate to receive a first enable and a second enable;
a first inverter coupled to an output of the OR-AND-INVERT gate;
a first NAND gate coupled to the output of the first inverter;
a second NAND gate coupled to the output of the OR-AND-INVERT gate; and
a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate.
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