CPC G06F 1/08 (2013.01) [G06F 1/324 (2013.01); G06F 1/3296 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
an event block circuit configured to:
monitor a bus connecting a plurality of processing devices; and
output an event signal, based on data transmitted through the bus;
a clock counter configured to count a number of clock signals received from a clock management circuit;
a plurality of performance counters configured to respectively count parameters related to a calculation of a workload, based on the event signal;
an interface configured to receive an operation signal from a dynamic voltage frequency scaling (DVFS) governor circuit and transmit the number of clock signals and the parameters to the DVFS governor circuit, the DVFS governor circuit being configured to determine an operation frequency and an operation voltage of each of the plurality of processing devices, based on the workload; and
a controller circuit configured to control operations of the event block circuit, the clock counter, and the plurality of performance counters, based on the operation signal.
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