US 11,917,838 B2
Semiconductor device
Shunpei Yamazaki, Tokyo (JP); Jun Koyama, Kanagawa (JP); and Kiyoshi Kato, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jan. 24, 2022, as Appl. No. 17/582,092.
Application 14/336,107 is a division of application No. 12/914,672, filed on Oct. 28, 2010, granted, now 8,896,042, issued on Nov. 25, 2014.
Application 17/582,092 is a continuation of application No. 16/944,289, filed on Jul. 31, 2020, granted, now 11,322,498.
Application 16/944,289 is a continuation of application No. 16/558,386, filed on Sep. 3, 2019, granted, now 10,811,417, issued on Oct. 20, 2020.
Application 16/558,386 is a continuation of application No. 15/615,873, filed on Jun. 7, 2017, granted, now 10,510,757, issued on Dec. 17, 2019.
Application 15/615,873 is a continuation of application No. 15/175,190, filed on Jun. 7, 2016, granted, now 9,685,447, issued on Jun. 20, 2017.
Application 15/175,190 is a continuation of application No. 14/804,478, filed on Jul. 21, 2015, granted, now 9,373,640, issued on Jun. 21, 2016.
Application 14/804,478 is a continuation of application No. 14/336,107, filed on Jul. 21, 2014, granted, now 9,105,511, issued on Aug. 11, 2015.
Claims priority of application No. 2009-251261 (JP), filed on Oct. 30, 2009.
Prior Publication US 2022/0149045 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 99/00 (2023.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/16 (2006.01); G11C 11/405 (2006.01); G11C 16/04 (2006.01); H01L 27/105 (2023.01); H01L 27/118 (2006.01); H10B 41/20 (2023.01); H10B 41/70 (2023.01); H10B 69/00 (2023.01); H01L 29/786 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01)
CPC H10B 99/00 (2023.02) [G11C 11/405 (2013.01); G11C 16/0433 (2013.01); H01L 27/105 (2013.01); H01L 27/11803 (2013.01); H01L 27/124 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/16 (2013.01); H01L 29/24 (2013.01); H01L 29/247 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01); H10B 41/20 (2023.02); H10B 41/70 (2023.02); H10B 69/00 (2023.02); G11C 2211/4016 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 29/7833 (2013.01); H10B 12/00 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor; and
a second transistor,
wherein a channel formation region of the first transistor comprises silicon,
wherein a channel formation region of the second transistor comprises an oxide semiconductor,
wherein a first insulating layer is provided over the channel formation region of the first transistor,
wherein a first gate electrode of the first transistor is provided over the first insulating layer,
wherein the first gate electrode of the first transistor is electrically connected to one of a source and a drain of the second transistor via a first opening in a second insulating layer, a second opening in a third insulating layer, a third opening in a fourth insulating layer, a fourth opening in a fifth insulating layer, a fifth opening in the fifth insulating layer, and a sixth opening in the fourth insulating layer,
wherein the one of the source and the drain of the second transistor is in contact with a top surface of a layer which comprises the oxide semiconductor,
wherein a second gate electrode of the second transistor is provided below the channel formation region of the second transistor, and
wherein, in a cross-sectional view, the layer which comprises the oxide semiconductor extends beyond an end portion of the second gate electrode.