US 11,917,818 B2
Memory device having vertical structure including a first wafer and a second wafer stacked on the first wafer
Sung Lae Oh, Icheon-si (KR); Sang Woo Park, Icheon-si (KR); Dong Hyuk Chae, Icheon-si (KR); and Ki Soo Kim, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 25, 2022, as Appl. No. 18/058,795.
Application 18/058,795 is a continuation of application No. 17/062,834, filed on Oct. 5, 2020, granted, now 11,538,820.
Claims priority of application No. 10-2020-0065284 (KR), filed on May 29, 2020.
Prior Publication US 2023/0100075 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/27 (2023.01); H01L 29/417 (2006.01); H01L 23/00 (2006.01); G11C 16/24 (2006.01); H10B 41/10 (2023.01); G11C 16/08 (2006.01); H01L 25/18 (2023.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); H01L 24/05 (2013.01); H01L 24/20 (2013.01); H01L 24/29 (2013.01); H01L 25/18 (2013.01); H01L 27/0296 (2013.01); H01L 29/0649 (2013.01); H01L 29/41741 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first wafer, and a second wafer stacked on and bonded to the first wafer,
wherein the first wafer comprises:
a cell structure including a memory cell array; and
a first logic structure disposed under the cell structure, and including a row control circuit,
wherein the second wafer comprises a second logic structure including a column control circuit,
wherein the memory cell array comprises a stack structure that is disposed on a source plate in a cell region and a slimming region, and bit lines disposed over the stack structure,
wherein the cell structure includes a source electrode that is coupled to the source plate through a contact structure passing through the stack structure, and
wherein the source electrode is disposed in the cell region of a wiring layer between the bit lines and the second wafer.