CPC H04N 19/513 (2014.11) [H04N 19/105 (2014.11); H04N 19/132 (2014.11); H04N 19/137 (2014.11); H04N 19/176 (2014.11)] | 18 Claims |
1. A video signal decoding device comprising:
a processor,
wherein the processor is configured to:
obtain a first motion vector of a current block corresponding to a first reference picture and a second motion vector of the current block corresponding to a second reference picture,
obtain a first picture order count (POC) difference representing a POC difference between the first reference picture and a current picture,
obtain a second POC difference representing a POC difference between the second reference picture and the current picture,
obtain at least one of a first correction value of the first motion vector and a second correction value of the second motion vector as a first value, based on a result of comparing the first POC difference and the second POC difference, wherein the first value is a specific offset,
obtain a first corrected motion vector by correcting the first motion vector based on the first correction value,
obtain a second corrected motion vector by correcting the second motion vector based on the second correction value, and
reconstruct the current block based on the first corrected motion vector and the second corrected motion vector,
wherein the first reference picture and the second reference picture are included in a first reference picture list and a second reference picture list, respectively, and
wherein the first reference picture list and the second reference picture are different from each other.
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