US 11,916,781 B2
System and method for facilitating efficient utilization of an output buffer in a network interface controller (NIC)
Partha Pratim Kundu, Palo Alto, CA (US); and David Charles Hewson, Bristol (GB)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Appl. No. 17/594,624
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
PCT Filed Mar. 23, 2020, PCT No. PCT/US2020/024242
§ 371(c)(1), (2) Date Oct. 25, 2021,
PCT Pub. No. WO2020/236269, PCT Pub. Date Nov. 26, 2020.
Claims priority of provisional application 62/852,273, filed on May 23, 2019.
Claims priority of provisional application 62/852,203, filed on May 23, 2019.
Claims priority of provisional application 62/852,289, filed on May 23, 2019.
Prior Publication US 2022/0255884 A1, Aug. 11, 2022
Int. Cl. H04L 49/9005 (2022.01); H04L 49/90 (2022.01); H04L 49/9047 (2022.01); G06F 13/40 (2006.01); H04L 45/28 (2022.01); H04L 45/028 (2022.01); H04L 45/125 (2022.01); H04L 45/00 (2022.01); H04L 45/122 (2022.01); H04L 47/76 (2022.01); H04L 49/15 (2022.01); H04L 49/00 (2022.01); H04L 69/40 (2022.01); H04L 47/10 (2022.01); H04L 47/34 (2022.01); H04L 67/1097 (2022.01); G06F 13/16 (2006.01); H04L 45/021 (2022.01); H04L 47/12 (2022.01); G06F 13/42 (2006.01); H04L 47/2441 (2022.01); H04L 47/30 (2022.01); H04L 47/62 (2022.01); H04L 47/24 (2022.01); G06F 13/38 (2006.01); H04L 45/745 (2022.01); H04L 47/2483 (2022.01); H04L 47/629 (2022.01); H04L 47/80 (2022.01); H04L 49/101 (2022.01); H04L 45/12 (2022.01); H04L 47/122 (2022.01); G06F 12/1036 (2016.01); G06F 15/173 (2006.01); H04L 43/10 (2022.01); H04L 45/42 (2022.01); H04L 47/11 (2022.01); G06F 12/0862 (2016.01); G06F 12/1045 (2016.01); H04L 47/32 (2022.01); G06F 9/54 (2006.01); G06F 13/14 (2006.01); G06F 9/50 (2006.01); H04L 47/22 (2022.01); H04L 47/52 (2022.01); H04L 47/6275 (2022.01); H04L 45/24 (2022.01); H04L 45/7453 (2022.01); H04L 45/16 (2022.01); H04L 69/22 (2022.01); H04L 47/762 (2022.01); H04L 47/78 (2022.01); H04L 47/20 (2022.01); H04L 1/00 (2006.01); H04L 43/0876 (2022.01); H04L 47/2466 (2022.01); H04L 47/625 (2022.01); H04L 69/28 (2022.01)
CPC H04L 45/28 (2013.01) [G06F 9/505 (2013.01); G06F 9/546 (2013.01); G06F 12/0862 (2013.01); G06F 12/1036 (2013.01); G06F 12/1063 (2013.01); G06F 13/14 (2013.01); G06F 13/16 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 15/17331 (2013.01); H04L 1/0083 (2013.01); H04L 43/0876 (2013.01); H04L 43/10 (2013.01); H04L 45/021 (2013.01); H04L 45/028 (2013.01); H04L 45/122 (2013.01); H04L 45/123 (2013.01); H04L 45/125 (2013.01); H04L 45/16 (2013.01); H04L 45/20 (2013.01); H04L 45/22 (2013.01); H04L 45/24 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 45/46 (2013.01); H04L 45/566 (2013.01); H04L 45/70 (2013.01); H04L 45/745 (2013.01); H04L 45/7453 (2013.01); H04L 47/11 (2013.01); H04L 47/12 (2013.01); H04L 47/122 (2013.01); H04L 47/18 (2013.01); H04L 47/20 (2013.01); H04L 47/22 (2013.01); H04L 47/24 (2013.01); H04L 47/2441 (2013.01); H04L 47/2466 (2013.01); H04L 47/2483 (2013.01); H04L 47/30 (2013.01); H04L 47/32 (2013.01); H04L 47/323 (2013.01); H04L 47/34 (2013.01); H04L 47/39 (2013.01); H04L 47/52 (2013.01); H04L 47/621 (2013.01); H04L 47/626 (2013.01); H04L 47/629 (2013.01); H04L 47/6235 (2013.01); H04L 47/6275 (2013.01); H04L 47/76 (2013.01); H04L 47/762 (2013.01); H04L 47/781 (2013.01); H04L 47/80 (2013.01); H04L 49/101 (2013.01); H04L 49/15 (2013.01); H04L 49/30 (2013.01); H04L 49/3009 (2013.01); H04L 49/3018 (2013.01); H04L 49/3027 (2013.01); H04L 49/90 (2013.01); H04L 49/9005 (2013.01); H04L 49/9021 (2013.01); H04L 49/9036 (2013.01); H04L 49/9047 (2013.01); H04L 67/1097 (2013.01); H04L 69/22 (2013.01); H04L 69/40 (2013.01); G06F 2212/50 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/3808 (2013.01); H04L 69/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A network interface controller (NIC), comprising:
an output buffer comprising a plurality of cells, wherein a respective cell is a unit of storage in the output buffer;
a host interface to receive a command from a host device;
an injector logic block to generate a packet based on the command; and
an allocation logic block to:
determine whether the packet is a multi-cell packet;
in response to determining that the packet is a multi-cell packet, wherein a first data structure comprises entries for a plurality of packet groups, wherein each packet group corresponds to a distinct maximum packet size of a plurality of maximum packet sizes;
determine, for the packet based on a size of the packet, a packet group which corresponds to a smallest of the maximum packet sizes that can accommodate the packet;
allocate, based on an entry in the first data structure for the determined packet group, a virtual index for the packet;
reserve, for the packet based on the size of the packet, a set of cells in the output buffer;
store, in the entry in the first data structure for the determined packet group: the virtual index for the packet; and a set of physical indices of the reserved cells, wherein the physical indices are stored in slots of the entry;
insert the packet into the reserved cells of the output buffer; and
responsive to inserting the packet into the reserved cells of the output buffer, store, in a second data structure: a packet handle associated with the packet; offset information associated with the virtual index; and an identifier of a message-fragmenting unit selected for forwarding the packet.