US 11,916,568 B2
Sampling circuit with a hierarchical time step generator
Marcel A. Kossel, Reichenburg (CH); Pier Andrea Francese, Adliswil (CH); Abdullah Serdar Yonar, Zurich (CH); Mridula Prathapan, Adliswil (CH); and Thomas Morf, Switzerland (CH)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 1, 2022, as Appl. No. 17/652,960.
Prior Publication US 2023/0283290 A1, Sep. 7, 2023
Int. Cl. H03M 1/50 (2006.01); H03K 5/135 (2006.01)
CPC H03M 1/50 (2013.01) [H03K 5/135 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A sampling circuit configured for digitizing an input signal, wherein said sampling circuit comprises:
a time-based analog-to-digital converter; and
a hierarchical time step generator comprising multiple levels, wherein said hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal, wherein said time-based analog-to-digital converter is configured to be controlled to digitize said input signal by said multiphase clock signals from said hierarchical time step generator;
wherein said hierarchical time step generator comprises:
a first level comprising a time step generator configured to generate first level clock signals in response to receiving said reference clock signal;
a second level comprising a phase interpolator circuit configured to generate multiple second level clock signals between each of said multiple first level clock signals; and
a third level comprising a device sampling phase generator configured to generate said multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of said second level clock signals.