US 11,916,516 B2
Low power operational amplifier trim offset circuitry
Nitin Agarwal, Bangalore (IN); Kunal Karanjkar, Bangalore (IN); and Venkata Ramanan, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 17, 2023, as Appl. No. 18/155,261.
Application 18/155,261 is a continuation of application No. 16/701,629, filed on Dec. 3, 2019, granted, now 11,558,013.
Prior Publication US 2023/0155553 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/02 (2006.01); H03F 3/45 (2006.01); H03M 1/66 (2006.01)
CPC H03F 1/0211 (2013.01) [H03F 3/45197 (2013.01); H03M 1/66 (2013.01); H03F 2200/375 (2013.01); H03F 2203/45044 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a reference circuit comprising a first reference voltage node and a second reference voltage node;
a digital-to-analog conversion (DAC) circuit comprising a plurality of transistor pairs, wherein each transistor pair of the plurality of transistor pairs comprises a first transistor and a second transistor, wherein a source terminal of the first transistor is coupled to a source terminal of the second transistor, wherein a gate terminal of the first transistor is coupled to a first pair of switches, wherein a gate terminal of the second transistor is coupled to a second pair of switches, wherein a first switch of the first pair of switches is coupled to a first node, wherein a second switch of the first pair of switches is coupled to a second node, wherein a first switch of the second pair of switches is coupled to the first node, wherein a second switch of the second pair of switches is coupled to the second node;
a third switch coupled to the first node and to the first reference voltage node; and
a fourth switch coupled to the second node and to the second reference voltage node.