CPC H01L 29/66553 (2013.01) [H01L 21/02167 (2013.01); H01L 21/02211 (2013.01); H01L 21/0228 (2013.01); H01L 21/02603 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4983 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a plurality of nanostructures surrounded by a gate dielectric, wherein each one of the plurality of nanostructures has a constant thickness; and
an inner spacer extending between adjacent ones of the plurality of nanostructures, the inner spacer having a dished surface, the dished surface having a depth of less than about 4.3 nm.
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