US 11,916,127 B2
Multi-layer electrode to improve performance of ferroelectric memory device
Yi Yang Wei, Hsinchu (TW); Bi-Shen Lee, Hsinchu (TW); Hsin-Yu Lai, Hsinchu (TW); Hai-Dang Trinh, Hsinchu (TW); Hsing-Lien Lin, Hsin-Chu (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 16, 2021, as Appl. No. 17/349,273.
Prior Publication US 2022/0406916 A1, Dec. 22, 2022
Int. Cl. H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 49/02 (2006.01); H10B 51/30 (2023.01); H10B 53/00 (2023.01)
CPC H01L 29/516 (2013.01) [H01L 28/57 (2013.01); H01L 28/65 (2013.01); H01L 28/75 (2013.01); H01L 29/40111 (2019.08); H10B 51/30 (2023.02); H10B 53/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a non-oxidized first bottom electrode layer over a substrate and a second bottom electrode layer over the non-oxidized first bottom electrode layer, wherein the second bottom electrode layer has a greater corrosion potential than the non-oxidized first bottom electrode layer, wherein the non-oxidized first bottom electrode layer directly contacts the second bottom electrode layer;
forming a ferroelectric switching layer over the second bottom electrode layer, wherein the second bottom electrode layer directly contacts the ferroelectric switching layer;
forming a second top electrode layer over the ferroelectric switching layer and a first top electrode layer over the second top electrode layer, wherein the second top electrode layer has a greater corrosion potential than the first top electrode layer;
performing a first patterning process on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode; and
performing a second patterning process on the non-oxidized first bottom electrode layer and the second bottom electrode layer to define a multi-layer bottom electrode.