US 11,916,119 B2
Transistor with self-aligned gate and self-aligned source/drain terminal(s) and methods
Zhong-Xiang He, Essex Junction, VT (US); Jeonghyun Hwang, Ithaca, NY (US); Ramsey M. Hazbun, Colchester, VT (US); Brett T. Cucci, Colchester, VT (US); Ajay Raman, Essex Junction, VT (US); and Johnatan A. Kantarovsky, South Burlington, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Nov. 3, 2021, as Appl. No. 17/517,738.
Prior Publication US 2023/0139011 A1, May 4, 2023
Int. Cl. H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/41783 (2013.01) [H01L 29/401 (2013.01); H01L 29/42376 (2013.01); H01L 29/6656 (2013.01); H01L 29/66462 (2013.01); H01L 29/66553 (2013.01); H01L 29/7786 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a gate comprising:
a first gate section on a barrier layer above a channel layer; and
a second gate section on the first gate section;
a source-side gate sidewall spacer positioned laterally adjacent to the first gate section, wherein the second gate section extends over the source-side gate sidewall spacer;
a source terminal comprising:
a first source region extending through the barrier layer, wherein the first source region has a proximal portion positioned laterally immediately adjacent to a lower portion of the source-side gate sidewall spacer and further has a distal portion; and
a second source region on the distal portion of the first source region; and
a source-side dielectric liner on the proximal portion of the first source region positioned laterally immediately adjacent to an upper portion of the source-side gate sidewall spacer, wherein the source-side dielectric liner is further positioned laterally between the second gate section and the second source region.