US 11,916,107 B2
Semiconductor device and manufacturing method thereof
Chun Hsiung Tsai, Xinpu Township (TW); Chih-Hsin Ko, Fongshan (TW); Clement Hsing Jen Wann, Carmel, NY (US); and Ya-Yun Cheng, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 13, 2023, as Appl. No. 18/097,057.
Application 18/097,057 is a continuation of application No. 16/856,817, filed on Apr. 23, 2020, granted, now 11,557,650, issued on Jan. 17, 2023.
Application 16/856,817 is a continuation in part of application No. 16/731,767, filed on Dec. 31, 2019, granted, now 11,393,713, issued on Jul. 19, 2022.
Claims priority of provisional application 62/955,871, filed on Dec. 31, 2019.
Claims priority of provisional application 62/837,519, filed on Apr. 23, 2019.
Prior Publication US 2023/0154980 A1, May 18, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/66553 (2013.01); H01L 29/66568 (2013.01); H01L 21/26513 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device including a FET, comprising:
an isolation insulating layer disposed in a trench of a substrate;
a gate dielectric layer disposed over a channel region of the substrate;
a gate electrode disposed over the gate dielectric layer;
a source and a drain disposed adjacent to the channel region; and
an air spacer formed in a space below the source,
wherein an impurity containing region containing an impurity in an amount higher than the substrate is disposed between the space and the substrate.