US 11,916,068 B2
Type III-V semiconductor substrate with monolithically integrated capacitor
Hyeongnam Kim, Chandler, AZ (US); and Mohamed Imam, Chandler, AZ (US)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Oct. 31, 2022, as Appl. No. 17/977,875.
Application 17/977,875 is a division of application No. 17/196,258, filed on Mar. 9, 2021, granted, now 11,545,485.
Prior Publication US 2023/0049654 A1, Feb. 16, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 27/06 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 27/0605 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor die comprising a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction; and
a capacitor monolithically formed in the semiconductor die,
wherein a dielectric medium of the capacitor comprises a first section of the barrier layer.