US 11,915,783 B2
Semiconductor device related to operation of internal circuits
Gi Moon Hong, Icheon-si (KR); and Dong Yoon Ka, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 15, 2022, as Appl. No. 17/695,613.
Claims priority of application No. 10-2022-0001199 (KR), filed on Jan. 4, 2022.
Prior Publication US 2023/0215476 A1, Jul. 6, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/10 (2006.01)
CPC G11C 7/1069 (2013.01) [G11C 7/22 (2013.01); G11C 8/10 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank; and
a data control circuit configured to:
generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank, and
control the output of the core data based on the switching signal,
wherein the core data based on the dummy column address when the read operation is not performed for the bank.