CPC G11C 7/065 (2013.01) [G11C 7/106 (2013.01); G11C 7/1039 (2013.01); G11C 7/1087 (2013.01)] | 16 Claims |
1. A semiconductor memory device comprising:
a core unit including a first memory cell group and a second memory cell group; and
a control circuit configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data via different portions of external terminals in parallel, the first address corresponding to the first memory cell group, the second address corresponding to the second memory cell group, the designation of the second address being made after the designation of the first address, the third data corresponding to the read first data, and the fourth data corresponding to the read second data.
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