US 11,915,778 B2
Semiconductor memory device outputting data from memory cell groups in parallel and system
Daisuke Arizono, Yokohama (JP); Akio Sugahara, Yokohama (JP); Mitsuhiro Abe, Kawasaki (JP); and Mitsuaki Honma, Fujisawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 15, 2022, as Appl. No. 17/654,890.
Claims priority of application No. 2021-163427 (JP), filed on Oct. 4, 2021.
Prior Publication US 2023/0109388 A1, Apr. 6, 2023
Int. Cl. G11C 16/06 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/065 (2013.01) [G11C 7/106 (2013.01); G11C 7/1039 (2013.01); G11C 7/1087 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a core unit including a first memory cell group and a second memory cell group; and
a control circuit configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data via different portions of external terminals in parallel, the first address corresponding to the first memory cell group, the second address corresponding to the second memory cell group, the designation of the second address being made after the designation of the first address, the third data corresponding to the read first data, and the fourth data corresponding to the read second data.