US 11,915,776 B2
Error avoidance based on voltage distribution parameters of block families
Michael Sheperek, Longmont, CO (US); Kishore Kumar Muchherla, San Jose, CA (US); Shane Nowell, Boise, ID (US); Mustafa N Kaynak, San Diego, CA (US); and Larry J Koudele, Erie, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/943,123.
Application 17/943,123 is a continuation of application No. 17/217,780, filed on Mar. 30, 2021, granted, now 11,443,830.
Prior Publication US 2023/0012855 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G11C 16/26 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/56008 (2013.01) [G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
13. A system comprising:
a memory; and
a processing device communicably coupled to the memory, the processing device to perform operations comprising:
receiving a request to read data from a block of the memory;
determining a voltage distribution parameter value associated with the block of the memory, wherein the voltage distribution parameter value is based on a feature of a corresponding voltage distribution associated with a plurality of memory cells of the block; and
determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory.