US 11,915,765 B2
Semiconductor storage device
Kazunori Hirayama, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 2, 2022, as Appl. No. 17/979,360.
Application 17/979,360 is a continuation of application No. 17/183,796, filed on Feb. 24, 2021, granted, now 11,521,685.
Claims priority of application No. 2020-120115 (JP), filed on Jul. 13, 2020.
Prior Publication US 2023/0047685 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit including a data latch, the first circuit configured to perform writing of data to a memory using the data latch and reading of data from the memory using the data latch; and
a second circuit configured to execute a sampling process by which sampling data is collected from a predetermined node of the first circuit and stored in the data latch,
wherein the sampling process is not executed during a period in which the data latch is used for the writing of data and the reading of data.