CPC G11C 16/10 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/3454 (2013.01)] | 18 Claims |
1. A memory device, comprising:
a memory structure including at least one non-volatile memory cell configured to store multi-bit data; and
a controller configured to:
perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell during a data program operation, the data program operation including applying a plurality of program pulses to program multi-bit data to the at least one non-volatile memory cell and the first program pulse being one of the plurality of program pulses,
determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and
change at least one of a level of a first control voltage based on the program mode, the first control voltage applied to a drain select line (DSL) coupled to the at least one non-volatile memory cell,
wherein the program mode corresponding to a second program pulse applied after the first program pulse is determined as one selected from a first mode, a second mode, and a third mode, the first mode to apply the second program pulse to change or adjust a threshold voltage of the at least one non-volatile memory cell by a first level which is equal to, or larger than, that caused by the first program pulse; the second mode to apply the second program pulse to change or adjust the threshold voltage of the at least one non-volatile memory cell by a second level which is smaller than that caused by the first program pulse; and the third mode to apply the second program pulse to the at least one non-volatile memory cell of which a change of the threshold voltage is inhibited.
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