US 11,915,760 B2
Semiconductor storage device
Sanad Bushnaq, Yokohama Kanagawa (JP); Noriyasu Kumazaki, Kawasaki Kanagawa (JP); and Masashi Yamaoka, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Apr. 12, 2023, as Appl. No. 18/299,505.
Application 17/480,858 is a division of application No. 16/557,754, filed on Aug. 30, 2019, granted, now 11,152,069, issued on Oct. 19, 2021.
Application 18/299,505 is a continuation of application No. 17/480,858, filed on Sep. 21, 2021, granted, now 11,657,874.
Claims priority of application No. 2018-238456 (JP), filed on Dec. 20, 2018.
Prior Publication US 2023/0253045 A1, Aug. 10, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); H10B 41/27 (2023.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); H10B 41/27 (2023.02); G11C 16/10 (2013.01); G11C 16/26 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor storage device, comprising:
a first memory block including a first memory string including a plurality of memory cell transistors connected in series, the plurality of memory cell transistors including a first memory transistor and a second memory transistor;
a plurality of word lines connected to gates of the memory cell transistors, respectively, the plurality of word lines including a first word line connected to a gate of the first memory transistor and a second word line connected to a gate of the second memory transistor;
a first source line connected to one end of the first memory string;
a first connection transistor having one end connected to the first word line and the other end connected to the first source line; and
a second connection transistor having one end connected to the second word line and the other end connected to the first source line.