US 11,915,759 B2
Memory system for restraining threshold variation to improve data reading
Masanobu Shirakawa, Chigasaki (JP); Marie Takada, Yokohama (JP); Tsukasa Tokutomi, Kamakura (JP); Yoshihisa Kojima, Kawasaki (JP); and Kiichi Tachi, Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 20, 2021, as Appl. No. 17/556,663.
Application 17/556,663 is a continuation of application No. 17/014,677, filed on Sep. 8, 2020, granted, now 11,238,936.
Application 17/014,677 is a continuation of application No. 16/697,540, filed on Nov. 27, 2019, granted, now 10,803,953, issued on Oct. 13, 2020.
Application 16/697,540 is a continuation of application No. 15/916,538, filed on Mar. 9, 2018, granted, now 10,541,030, issued on Jan. 21, 2020.
Claims priority of application No. 2017-180531 (JP), filed on Sep. 20, 2017.
Prior Publication US 2022/0115070 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/08 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory including:
a first block including a plurality of first memory cells;
a second block including a plurality of second memory cells;
a plurality of first word lines coupled to the first memory cells;
a plurality of second word lines coupled to the second memory cells; and
a driver circuit capable of applying voltages to the first word lines via a first row decoder and applying voltages to the second word lines via a second row decoder; and
a controller configured to control the semiconductor memory, wherein
in response to a data read command for data stored in the first block or the second block, the data read command being issued by the controller to the semiconductor memory, a first voltage is applied to a selected word line, and a second voltage larger than the first voltage is applied to unselected word lines, and
in response to a first command, the first command being issued by the controller to the semiconductor memory, the driver circuit is configured to apply a third voltage smaller than the first voltage to the plurality of first word lines via the first row decoder and to apply the third voltage to the plurality of second word lines via the second row decoder.