US 11,915,756 B2
Nonvolatile semiconductor memory device
Yasuhiro Shiino, Yokohama (JP); and Eietsu Takahashi, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on May 2, 2022, as Appl. No. 17/734,359.
Application 17/734,359 is a continuation of application No. 17/064,053, filed on Oct. 6, 2020, granted, now 11,355,193.
Application 17/064,053 is a continuation of application No. 16/574,637, filed on Sep. 18, 2019, granted, now 10,832,777, issued on Nov. 10, 2020.
Application 16/574,637 is a continuation of application No. 16/025,429, filed on Jul. 2, 2018, granted, now 10,460,806, issued on Oct. 29, 2019.
Application 16/025,429 is a continuation of application No. 15/706,250, filed on Sep. 15, 2017, granted, now 10,043,579, issued on Aug. 7, 2018.
Application 15/706,250 is a continuation of application No. 15/345,585, filed on Nov. 8, 2016, granted, now 9,805,798, issued on Oct. 31, 2017.
Application 15/345,585 is a continuation of application No. 14/945,569, filed on Nov. 19, 2015, granted, now 9,530,510, issued on Dec. 27, 2016.
Application 14/945,569 is a continuation of application No. 14/295,923, filed on Jun. 4, 2014, granted, now 9,214,237, issued on Dec. 15, 2015.
Application 14/295,923 is a continuation of application No. 14/066,875, filed on Oct. 30, 2013, granted, now 8,787,091, issued on Jul. 22, 2014.
Application 14/066,875 is a continuation of application No. 13/457,560, filed on Apr. 27, 2012, granted, now 8,599,617, issued on Dec. 3, 2013.
Application 13/457,560 is a continuation of application No. 12/878,624, filed on Sep. 9, 2010, granted, now 8,199,579, issued on Jun. 12, 2012.
Claims priority of application No. 2009-214143 (JP), filed on Sep. 16, 2009; and application No. 2010-028109 (JP), filed on Feb. 10, 2010.
Prior Publication US 2022/0262439 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/00 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/08 (2006.01); G11C 16/28 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 11/5635 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/28 (2013.01); G11C 16/3404 (2013.01); G11C 16/344 (2013.01); G11C 16/3413 (2013.01); G11C 16/3445 (2013.01); G11C 16/3463 (2013.01); G11C 2211/5621 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device, comprising:
a memory string including a plurality of nonvolatile memory cells for data storage which are capable of storing multi-bit data connected in series,
a first dummy cell which is not used for data storage provided at at least a first end of the memory string,
select transistors connected to both ends of the memory string respectively,
word lines connected to control gate electrodes of the memory cells for data storage;
a first dummy word line connected to a control gate electrode of the first dummy cell;
a bit line connected to the first end of the memory string;
a source line connected to a second end of the memory string; and
a control circuit configured to perform an erasing operation by applying an erasing voltage to the memory string,
wherein before a pre-program operation before an erasing operation to the nonvolatile memory cell, the control circuit determines whether or not a certain condition is satisfied.