US 11,915,748 B2
Semiconductor memory device, memory system, and write method
Noboru Shibata, Kawasaki Kanagawa (JP); and Yasuyuki Matsuda, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 22, 2023, as Appl. No. 18/112,507.
Application 17/158,567 is a division of application No. 16/529,644, filed on Aug. 1, 2019, granted, now 10,943,651, issued on Mar. 9, 2021.
Application 18/112,507 is a continuation of application No. 17/874,968, filed on Jul. 27, 2022, granted, now 11,621,039.
Application 17/874,968 is a continuation of application No. 17/158,567, filed on Jan. 26, 2021, granted, now 11,437,095, issued on Sep. 6, 2022.
Application 16/529,644 is a continuation in part of application No. 16/275,776, filed on Feb. 14, 2019, abandoned.
Claims priority of application No. 2018-146833 (JP), filed on Aug. 3, 2018.
Prior Publication US 2023/0206998 A1, Jun. 29, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 11/408 (2006.01); G11C 16/08 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/4085 (2013.01); G11C 11/565 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory device having a first memory region including a first memory cell capable of holding at least 4-bit data and a second memory region including a plurality of second memory cells capable of holding at least 1-bit data;
a controller configured to control a first write operation and a second write operation based on the 4-bit data in the semiconductor memory device; and
at least one wiring connecting the semiconductor memory device and the controller,
wherein:
the controller includes a conversion circuit which converts the 4-bit data into n-bit data, with n being an integer,
the semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted n-bit data and data written in the first memory cell by the first write operation,
when the controller detects power shutdown, the conversion circuit converts the 4-bit data used for the first write operation into the n-bit data, and
the controller instructs the semiconductor memory device to write each of the n-bit data in different second memory cells of the plurality of second memory cells.