US 11,915,745 B2
Low standby leakage implementation for static random access memory
Sudarshan Kumar, Barauni (IN); Mayank Tayal, Bangalore (IN); and Sagar Vidya Reddy, Santa Clara, CA (US)
Assigned to DXCorr Design Inc., Sunnyvale, CA (US)
Filed by DXCorr Design Inc., Sunnyvale, CA (US)
Filed on Sep. 15, 2021, as Appl. No. 17/475,386.
Prior Publication US 2023/0080591 A1, Mar. 16, 2023
Int. Cl. G11C 11/419 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); G11C 11/418 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory architecture for optimizing leakage currents in standby mode, comprising:
a plurality of local IO slices in a first direction, wherein each of the plurality of local IO slice comprises:
one or more bitline pair(s) running in a second direction for reading and writing in a memory bitcell; and
a plurality of power supply rails running in the second direction;
a plurality of memory bitcell arrays running in the first direction and the second direction, wherein the plurality of memory bitcell arrays comprises a plurality of the memory bitcells and wherein the plurality of the memory bitcells have a common bitline pair and common power supply per column; and
a plurality of memory segments configured to operate in one or more modes of operations, wherein the plurality of memory segments comprise a plurality of decoder slices, wherein each of the plurality of decoder slices comprises:
a plurality of word lines running in the first direction;
at least one array power header configured for controlling leakage currents;
a retention header, wherein the at least one array power header, the retention header, and a pmos transistor connected to the retention header, are configured to control wake-up current and wake-up time of the plurality of memory segments from deep sleep retention mode to normal mode; and
wherein each of the plurality of power supply rails running in the second direction are segmented within the plurality of the decoder slices to form one or more segmented power supply nodes.