US 11,915,733 B2
Memory devices, circuits and methods of adjusting a sensing current for the memory device
Win-San Khwa, Taipei (TW); Jui-Jen Wu, Hsinchu (TW); Jen-Chieh Liu, Hsinchu (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 17, 2022, as Appl. No. 17/577,040.
Claims priority of provisional application 63/225,405, filed on Jul. 23, 2021.
Prior Publication US 2023/0028413 A1, Jan. 26, 2023
Int. Cl. G11C 11/16 (2006.01)
CPC G11C 11/1673 (2013.01) [G11C 11/161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a sense amplifier;
a first clamping circuit including a plurality of first clamping branches coupled in parallel between the sense amplifier and a memory array;
a second clamping circuit including a plurality of second clamping branches coupled in parallel between the sense amplifier and a reference array; and
a feedback circuit configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to output data outputted by the sense amplifier.