| CPC G09G 3/3266 (2013.01) [G09G 2300/0852 (2013.01)] | 14 Claims |
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1. A display device comprising:
a display panel having a plurality of sub-pixels defined thereon, the plurality of sub-pixels being connected to a plurality of scan lines and a plurality of data lines; and
a gate driver comprising a plurality of stages for supplying first and second scan signals at a high-level to each of the plurality of scan lines,
wherein each of the plurality of stages comprises:
a first output unit for outputting the first scan signal;
a second output unit for outputting the second scan signal;
a logic unit connected to the first output unit and the second output unit;
a low-clock signal line for outputting a low-clock signal at a low-level and connected to the logic unit; and
a high-clock signal line for outputting a high-clock signal at a high-level and connected to the second output unit,
wherein the first output unit comprises:
a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a second gate-low line and a first output terminal from which the first scan signal is output; and
a second transistor having a gate electrode connected to a QB node, and a source electrode and a drain electrode connected between a gate-high line and the first output terminal, and
wherein the second output unit includes:
a six transistor having a gate electrode connected to the first output terminal, and a source electrode and a drain electrode connected between a first gate-low line and a second output terminal from which the second scan signal is output.
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