CPC G06F 3/0634 (2013.01) [G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7206 (2013.01); Y02D 10/00 (2018.01)] | 6 Claims |
1. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a read and write circuit and a plurality of data blocks, the flash memory controller comprising:
a communication interface for receiving data from a host device; and
a processing circuit, coupled with the communication interface and the flash memory module, for receiving data from a host device;
wherein the processing circuit determines if the data received from the host device is cold data or hot data; and if the processing circuit determines that the data is the cold data, the processing circuit uses a two-bit-per-cell mode or a three-bit-per-cell mode to write the data into a one of the data blocks; and if the processing circuit determines that the data is the hot data, the processing circuit uses a one-bit-per-cell mode to write the data into another one of the data blocks.
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