CPC G06F 13/4221 (2013.01) [G06F 13/1668 (2013.01); G06F 13/409 (2013.01)] | 11 Claims |
1. A memory system comprising:
a board including a terminal part, the terminal part being connectable to an outside connector;
a memory controller on the board; and
a semiconductor memory on the board, the semiconductor memory being connected to the memory controller, wherein
the terminal part includes a first terminal, a second terminal, and a third terminal,
the memory controller includes a first port, a second port, and a third port, the first port being connected to the first terminal, the second port being connected to the second terminal, the third port being connected to the third terminal,
when a signal input to the third port or a command received from the outside of the memory system satisfies a first condition, the memory controller is configured to use the first port as a first signal port for a first signal and to use the second port as a second signal port for a second signal different from the first signal, and
when the signal input to the third port or the command received from the outside of the memory system satisfies a second condition different from the first condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.
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