US 11,914,544 B2
Memory system, method of controlling memory system, and host system
Nana Kawamoto, Yokohama Kanagawa (JP); and Naoki Kimura, Ebina Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 15, 2022, as Appl. No. 17/841,390.
Claims priority of application No. 2022-045462 (JP), filed on Mar. 22, 2022.
Prior Publication US 2023/0305986 A1, Sep. 28, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 13/1668 (2013.01); G06F 13/409 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory system comprising:
a board including a terminal part, the terminal part being connectable to an outside connector;
a memory controller on the board; and
a semiconductor memory on the board, the semiconductor memory being connected to the memory controller, wherein
the terminal part includes a first terminal, a second terminal, and a third terminal,
the memory controller includes a first port, a second port, and a third port, the first port being connected to the first terminal, the second port being connected to the second terminal, the third port being connected to the third terminal,
when a signal input to the third port or a command received from the outside of the memory system satisfies a first condition, the memory controller is configured to use the first port as a first signal port for a first signal and to use the second port as a second signal port for a second signal different from the first signal, and
when the signal input to the third port or the command received from the outside of the memory system satisfies a second condition different from the first condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.