US 11,914,526 B2
Memory controller for RPMB-inclusive memory device, operating method thereof and electronic device including the same
Kwang Su Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 19, 2022, as Appl. No. 18/083,572.
Application 18/083,572 is a continuation of application No. 16/889,377, filed on Jun. 1, 2020, granted, now 11,580,033.
Application 16/889,377 is a continuation of application No. 16/114,688, filed on Aug. 28, 2018, granted, now 10,671,544, issued on Jun. 2, 2020.
Claims priority of application No. 10-2018-0012287 (KR), filed on Jan. 31, 2018.
Prior Publication US 2023/0118843 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/14 (2006.01); G11C 16/22 (2006.01); G06F 21/79 (2013.01); G11C 7/24 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/14 (2013.01) [G06F 12/1458 (2013.01); G06F 21/79 (2013.01); G11C 7/24 (2013.01); G11C 16/22 (2013.01); G06F 12/0246 (2013.01); G06F 12/1433 (2013.01); G06F 2206/1014 (2013.01); G06F 2212/1052 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of operating a memory controller configured to control a memory device including a replay protected memory block (RPMB) requiring authenticated access, the method comprising:
receiving a first data packet for the RPMB from outside, wherein the first data packet includes a first authentication code and information regarding a request type indicating the request type of the first data packet is a write request;
receiving data for storing in the RPMB from the outside, after the receiving the first data packet; and
transmitting a second data packet, which includes
information regarding a response type indicating the response type of the second data packet is a write response.