US 11,914,474 B2
Efficient management of failed memory blocks in memory sub-systems
Tyler L. Betz, Meridian, ID (US); Andrew M. Kowles, Seattle, WA (US); and Adam J. Hieb, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 13, 2023, as Appl. No. 18/167,992.
Application 18/167,992 is a continuation of application No. 16/947,975, filed on Aug. 26, 2020, granted, now 11,579,968.
Prior Publication US 2023/0195572 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0644 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of physical memory segments, wherein each of the physical memory segments comprises a plurality of memory cells; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, performing one or more scanning operations associated with the physical memory segment to estimate a fraction of bad memory cells in at least a sub-plurality of memory cells of the physical memory segment; and
determining, based on a relationship of the estimated fraction of bad memory cells to one or more threshold fractions, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.