US 11,914,469 B2
Resiliency and performance for cluster memory
Marcos K. Aguilera, Mountain View, CA (US); Keerthi Kumar, Bangalore (IN); Pramod Kumar, Bangalore (IN); Pratap Subrahmanyam, Saratoga, CA (US); Sairam Veeraswamy, Coimbatore (IN); and Rajesh Venkatasubramanian, Palo Alto, CA (US)
Assigned to VMware, Inc., Palo Alto, CA (US)
Filed by VMware LLC, Palo Alto, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,345.
Claims priority of application No. 202141032022 (IN), filed on Jul. 16, 2021.
Prior Publication US 2023/0012999 A1, Jan. 19, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/0772 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a computing device comprising a processor and a memory; and
machine-readable instructions stored in the memory that, when executed by the processor, cause the computing device to at least:
split a local page into a plurality of subpages;
generate at least one parity subpage;
submit a write request for each of the plurality of subpages to a respective one of a plurality of memory hosts; and
submit an additional write request for the at least one parity subpage to an additional one of the plurality of memory hosts.