US 11,914,439 B2
Synchronous reset signal generation circuit and digital processing device
Hiromitsu Kimura, Kyoto (JP); and Yuji Kurotsuchi, Kyoto (JP)
Assigned to Rohm Co., Ltd., Kyoto (JP)
Appl. No. 17/600,702
Filed by Rohm Co., Ltd., Kyoto (JP)
PCT Filed Mar. 17, 2020, PCT No. PCT/JP2020/011758
§ 371(c)(1), (2) Date Oct. 1, 2021,
PCT Pub. No. WO2020/213334, PCT Pub. Date Oct. 22, 2020.
Claims priority of application No. 2019078607 (JP), filed on Apr. 17, 2019.
Prior Publication US 2022/0187887 A1, Jun. 16, 2022
Int. Cl. H03K 17/22 (2006.01); G06F 1/24 (2006.01); H03K 21/10 (2006.01)
CPC G06F 1/24 (2013.01) [H03K 21/10 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A synchronous reset signal generation circuit configured to generate a synchronous reset signal by synchronizing an asynchronous reset signal with a clock signal, the synchronous reset signal generation circuit comprising:
a synchronous reset signal output circuit
having L flip-flops connected in a cascade arrangement and
configured to output the synchronous reset signal from a final-stage flip-flop among the L flip-flops;
a first error determination signal output circuit
having M flip-flops connected in a cascade arrangement and
configured to output a first error determination signal from a final-stage flip-flop among the M flip-flops;
a second error determination signal output circuit
having N flip-flops connected in a cascade arrangement and
configured to output a second error determination signal from a final-stage flip-flop among the N flip-flops; and
a fault determination circuit configured to determine presence or absence of a fault in the synchronous reset signal generation circuit based on the synchronous reset signal, the first error determination signal, and the second error determination signal,
wherein
the first error determination signal is input to an initial-stage flip-flop among the N flip-flops,
the clock signal and the asynchronous reset signal are commonly input to the L, M, and N flip-flops, and
L, M, and N are integers fulfilling M≥2, L≥M+1, and M+N≥L+1 simultaneously.