US 11,914,416 B2
Transmitter circuit and method of operating same
Junyoung Park, Seongnam-si (KR); Joohwan Kim, Seoul (KR); Jindo Byun, Suwon-si (KR); Eunseok Shin, Seoul (KR); Hyunyoon Cho, Uiwang-si (KR); Youngdon Choi, Seoul (KR); and Junghwan Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 5, 2022, as Appl. No. 17/737,575.
Claims priority of application No. 10-2021-0067896 (KR), filed on May 26, 2021; and application No. 10-2021-0119857 (KR), filed on Sep. 8, 2021.
Prior Publication US 2022/0382317 A1, Dec. 1, 2022
Int. Cl. H03K 3/00 (2006.01); G06F 1/06 (2006.01); H03K 3/017 (2006.01); H03K 19/20 (2006.01)
CPC G06F 1/06 (2013.01) [H03K 3/017 (2013.01); H03K 19/20 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals, the transmitter circuit comprising:
a clock generator configured to generate first clock signals having different respective phases;
a multiplexer including a plurality of selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals; and
an output driver configured to generate the serial signal by amplifying a signal the output node,
wherein each selection circuit of the plurality of selection circuits comprises:
a first P-type transistor configured to precharge the output node in response to detecting a first parallel signal among the parallel signals having a first logic level and a second parallel signal among the parallel signals having the first logic level; and
a first N-type transistor configured to discharge the output node in response to detecting the first parallel signal having a second logic level and a second parallel signal having the second logic level.