CPC G03F 7/7065 (2013.01) [G03F 7/0045 (2013.01); G06F 17/15 (2013.01); G06F 30/23 (2020.01)] | 20 Claims |
1. A method, comprising:
using a calibrated lithographic model to generate a lithographic model output based on simulating a lithography process for an integrated circuit (IC) design layout;
extracting, by a processor, at least a chemical parameter from the lithographic model output, wherein the chemical parameter is an inhibitor concentration; and
using a calibrated defect rate model to predict a defect rate for the IC design layout based on the chemical parameter.
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