US 11,895,927 B2
Semiconductor memory device and fabrication method thereof
Chia-Chang Hsu, Kaohsiung (TW); Tang-Chun Weng, Chiayi (TW); Cheng-Yi Lin, Yilan County (TW); Yung-Shen Chen, Kaohsiung (TW); and Chia-Hung Lin, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on May 13, 2021, as Appl. No. 17/319,106.
Claims priority of application No. 202110446979.5 (CN), filed on Apr. 25, 2021.
Prior Publication US 2022/0344579 A1, Oct. 27, 2022
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate comprising a conductor region thereon;
an interlayer dielectric layer on the substrate;
a conductive via electrically connected to the conductor region, wherein the conductive via comprises a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer, wherein the upper portion has a rounded top surface, wherein the upper portion has a width that is equal to or smaller than a width of the lower portion; and
a storage structure conformally covering the rounded top surface.