US 11,895,871 B2
Light emitting device and electronic equipment including a light reflection layer, an insulation layer, and a plurality of pixel electrodes
Takeshi Koshihara, Matsumoto (JP); and Ryoichi Nozawa, Shiojiri (JP)
Assigned to SEIKO EPSON CORPORATION, Tokyo (JP)
Filed by SEIKO EPSON CORPORATION, Tokyo (JP)
Filed on May 20, 2022, as Appl. No. 17/749,757.
Application 14/823,656 is a division of application No. 14/455,566, filed on Aug. 8, 2014, granted, now 9,142,599, issued on Sep. 22, 2015.
Application 17/749,757 is a continuation of application No. 16/891,482, filed on Jun. 3, 2020, granted, now 11,374,077.
Application 16/891,482 is a continuation of application No. 16/057,026, filed on Aug. 7, 2018, granted, now 10,714,555, issued on Jul. 14, 2020.
Application 16/057,026 is a continuation of application No. 15/233,424, filed on Aug. 10, 2016, granted, now 10,074,708, issued on Sep. 11, 2018.
Application 15/233,424 is a continuation of application No. 14/823,656, filed on Aug. 11, 2015, granted, now 9,443,919, issued on Sep. 13, 2016.
Claims priority of application No. 2013-175339 (JP), filed on Aug. 27, 2013.
Prior Publication US 2022/0278184 A1, Sep. 1, 2022
Int. Cl. H10K 59/121 (2023.01); H10K 50/852 (2023.01); H10K 50/856 (2023.01); H10K 59/123 (2023.01); H10K 59/35 (2023.01); H10K 50/805 (2023.01); H10K 59/12 (2023.01); H10K 50/824 (2023.01); H10K 102/00 (2023.01); H10K 59/38 (2023.01); H10K 59/124 (2023.01); H10K 59/126 (2023.01); H10K 50/00 (2023.01); H10K 50/818 (2023.01); H10K 59/30 (2023.01)
CPC H10K 59/1213 (2023.02) [H10K 50/852 (2023.02); H10K 50/856 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 59/126 (2023.02); H10K 59/35 (2023.02); H10K 59/38 (2023.02); H10K 50/00 (2023.02); H10K 50/805 (2023.02); H10K 50/818 (2023.02); H10K 50/824 (2023.02); H10K 59/1201 (2023.02); H10K 59/30 (2023.02); H10K 59/351 (2023.02); H10K 2102/3026 (2023.02); H10K 2102/341 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A light emitting device comprising:
a transistor having a gate layer;
a capacitor;
an electrode;
a first pixel electrode disposed in a layer between the transistor and the electrode;
a light emission functional layer disposed in a layer between the electrode and the first pixel electrode;
a first conductive layer disposed in a layer between the first pixel electrode and the transistor, and configured to be supplied with a constant potential;
a second conductive layer disposed in a layer between the first conductive layer and the transistor, the second conductive layer electrically connected to the transistor;
a third conductive layer disposed in a layer between the second conductive layer and the transistor, the third conductive layer electrically connected to the capacitor;
a first insulating layer disposed in a layer between the first conductive layer and the second conductive layer, the first insulating layer including a first contact hole via which the first conducive layer is electrically connected to the second conducive layer; and
a second insulating layer disposed in a layer between the third conductive layer and the transistor, the second insulating layer including a second contact hole via which the third conducive layer is electrically connected to the gate layer, wherein
in a plan view, a region where the first pixel electrode contacts with the light emission functional layer overlaps with the first conductive layer, the second conductive layer, and the third conductive layer respectively, and
in a cross-sectional view, a width of the first contact hole is wider than a width of the second contact hole.