US 11,895,846 B2
Double-gated ferroelectric field-effect transistor
Abhishek A. Sharma, Portland, OR (US); Brian S. Doyle, Portland, OR (US); Ravi Pillarisetty, Portland, OR (US); Prashant Majhi, San Jose, CA (US); and Elijah V. Karpov, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 16, 2022, as Appl. No. 17/673,670.
Application 17/673,670 is a continuation of application No. 16/640,467, granted, now 11,289,509, previously published as PCT/US2017/054538, filed on Sep. 29, 2017.
Prior Publication US 2022/0181335 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H10B 51/30 (2023.01); G11C 11/22 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01)
CPC H10B 51/30 (2023.02) [G11C 11/223 (2013.01); H01L 29/516 (2013.01); H01L 29/7831 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A ferroelectric field-effect transistor (FeFET), comprising:
first and second gate electrodes;
source and drain regions;
a region between and physically connecting the source and drain regions, the region comprising semiconductor material;
a first gate dielectric between the region and the first gate electrode, the first gate dielectric comprising a ferroelectric dielectric, and the first gate dielectric having a first lateral width; and
a second gate dielectric between the region and the second gate electrode, the second gate dielectric having a second lateral width, the second lateral width different than the first lateral width.