US 11,895,832 B2
Memory integrated circuit
Yun-Feng Kao, Hsinchu (TW); Ming-Yen Chuang, Hsinchu (TW); Katherine H. Chiang, New Taipei (TW); and Chia-En Huang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 6, 2021, as Appl. No. 17/395,468.
Prior Publication US 2023/0041409 A1, Feb. 9, 2023
Int. Cl. H01L 29/786 (2006.01); G11C 11/40 (2006.01); H10B 12/00 (2023.01); G11C 11/4091 (2006.01)
CPC H10B 12/50 (2023.02) [G11C 11/4091 (2013.01); H01L 29/7869 (2013.01); H10B 12/315 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory integrated circuit, comprising:
a first memory array and a second memory array, laterally spaced apart from each other, and respectively comprising:
memory cells, each comprising an access transistor and a storage capacitor coupled to the access transistor;
bit lines, respectively coupled to a row of the memory cells; and
word lines, respectively coupled to a column of the memory cells; and
a driving circuit, disposed below the first and second memory arrays, and comprising sense amplifiers, wherein each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers,
wherein the first and second memory arrays are disposed at the same height with a spacing in between, and the bit lines coupled to the memory cells of the first and second memory arrays are connected to the input lines of the sense amplifiers through the spacing.