US 11,895,824 B2
Vertical 1T-1C DRAM array
Ravi Pillarisetty, Portland, OR (US); Van H. Le, Portland, OR (US); Gilbert Dewey, Hillsboro, OR (US); and Abhishek A Sharma, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 8, 2022, as Appl. No. 17/667,498.
Application 17/667,498 is a division of application No. 16/480,627, granted, now 11,289,490, previously published as PCT/US2017/025551, filed on Mar. 31, 2017.
Prior Publication US 2022/0165737 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/36 (2023.02) [H10B 12/056 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit comprising:
forming transistor bodies in a plurality rows on a substrate, each of the bodies comprising a first diffusion region, a second diffusion region and a channel of a transistor, wherein the second diffusion regions is on the first diffusion region and separated by the channel;
forming a masking material as a plurality of rows across the bodies;
etching the bodies through the masking material to define a width dimension of the transistor bodies, wherein the width dimension is defined by a width dimension of the masking material;
after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units comprising the width dimension and a length dimension defined by the patterning; and
replacing each of the plurality of individual masking units with a programmable element.