US 11,895,822 B2
Memory structure and forming method thereof
Yachao Xu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/435,640
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Apr. 12, 2021, PCT No. PCT/CN2021/086459
§ 371(c)(1), (2) Date Sep. 1, 2021,
PCT Pub. No. WO2021/208833, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 202010299480.1 (CN), filed on Apr. 16, 2020.
Prior Publication US 2023/0103424 A1, Apr. 6, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/033 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
a plurality of vertical transistors, the vertical transistors comprise silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction;
m bit lines, extending in the first direction and electrically connected to drains of all the vertical transistors in a same row, the drains are located below the silicon pillars; and
n word lines, extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in a same column;
the first direction and the second direction form a non-right angle.