	US 11,895,816 B2
	Bitcell architecture
Amit Chhabra, Noida (IN); and Brian Tracy Cline, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Dec. 4, 2020, as Appl. No. 17/112,479.
Prior Publication US 2022/0181331 A1, Jun. 9, 2022
Int. Cl. H01L 21/8238 (2006.01); H10B 10/00 (2023.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 27/02 (2006.01)

CPC H10B 10/12 (2023.02) [H01L 21/823871 (2013.01); H01L 23/528 (2013.01); H01L 27/0922 (2013.01)]

20 Claims

1. A device comprising:

multiple transistors arranged as a bitcell;

wherein the multiple transistors include multiple P-type transistors that are sequentially arranged in a P-over-P stack configuration,

wherein the multiple transistors include multiple N-type transistors that are sequentially arranged in an N-over-N stack configuration, and

wherein the multiple P-type transistors in the P-over-P stack configuration are disposed alongside the multiple N-type transistors in the N-over-N stack configuration.