US 11,895,773 B2
Circuit board structure
Shih-Lian Cheng, New Taipei (TW)
Assigned to Unimicron Technology Corp., Taoyuan (TW)
Filed by Unimicron Technology Corp., Taoyuan (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/853,933.
Claims priority of provisional application 63/279,661, filed on Nov. 15, 2021.
Claims priority of application No. 111120375 (TW), filed on Jun. 1, 2022.
Prior Publication US 2023/0156918 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/116 (2013.01) [H05K 1/0222 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/09509 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A circuit board structure, comprising:
a substrate having an opening and comprising a first dielectric layer, a second dielectric layer, a first inner circuit layer, a second inner circuit layer, and a conductive connection layer, wherein the opening penetrates through the first dielectric layer, the first dielectric layer has a first surface and a second surface opposite to each other, the first inner circuit layer is disposed on the first surface, and the second inner circuit layer is disposed on the second surface, the conductive connection layer covers an inner wall of the opening and connects the first inner circuit layer and the second inner circuit layer, the second dielectric layer fills the opening, and the second dielectric layer has a third surface and a fourth surface opposite to each other;
a third dielectric layer covering the first inner circuit layer and the third surface;
a fourth dielectric layer covering the second inner circuit layer and the fourth surface;
a first external circuit layer disposed on the third dielectric layer;
a second external circuit layer disposed on the fourth dielectric layer;
a conductive through hole penetrating through the third dielectric layer, the second dielectric layer, and the fourth dielectric layer, and connecting the first external circuit layer and the second external circuit layer electrically;
a first annular retaining wall disposed in the third dielectric layer, surrounding the conductive through hole, and connecting the first external circuit layer and the first inner circuit layer electrically; and
a second annular retaining wall disposed in the fourth dielectric layer, surrounds the conductive through hole, and connecting the second external circuit layer and the second inner circuit layer electrically.