CPC H04N 19/52 (2014.11) [H04N 19/119 (2014.11); H04N 19/176 (2014.11)] | 2 Claims |
1. A decoder, comprising:
circuitry; and
memory, wherein
using the memory, the circuitry, in operation, determines to perform a decoding mode from among candidates including a decoder-side motion vector refinement (DMVR) decoding mode and a partition decoding mode,
when the DMVR decoding mode is determined to be performed, the circuitry:
obtains a first motion vector for a first image block;
derives a second motion vector from the first motion vector using motion search; and
generates a prediction image for the first image block using the second motion vector; and
when the partition decoding mode is determined to be performed, the circuitry:
determines a plurality of partitions in a second image block;
obtains a third motion vector for each partition; and
generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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