US 11,895,323 B2
Encoder, decoder, encoding method, and decoding method
Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); Ryuichi Kanoh, Osaka (JP); Chong Soon Lim, Singapore (SG); Ru Ling Liao, Singapore (SG); Hai Wei Sun, Singapore (SG); Sughosh Pavan Shashidhar, Singapore (SG); Han Boon Teo, Singapore (SG); and Jing Ya Li, Singapore (SG)
Assigned to Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Nov. 22, 2022, as Appl. No. 18/058,057.
Application 18/058,057 is a continuation of application No. 18/057,440, filed on Nov. 21, 2022.
Application 18/057,440 is a continuation of application No. 18/056,963, filed on Nov. 18, 2022.
Application 18/056,963 is a continuation of application No. 18/056,542, filed on Nov. 17, 2022.
Application 18/056,542 is a continuation of application No. 18/056,136, filed on Nov. 16, 2022.
Application 18/056,136 is a continuation of application No. 17/323,936, filed on May 18, 2021, granted, now 11,558,635.
Application 17/323,936 is a continuation of application No. 16/942,601, filed on Jul. 29, 2020, granted, now 11,044,491, issued on Jun. 22, 2021.
Application 16/942,601 is a continuation of application No. PCT/JP2019/003072, filed on Jan. 30, 2019.
Claims priority of provisional application 62/623,841, filed on Jan. 30, 2018.
Prior Publication US 2023/0103036 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 11/02 (2006.01); H04N 19/52 (2014.01); H04N 19/119 (2014.01); H04N 19/176 (2014.01)
CPC H04N 19/52 (2014.11) [H04N 19/119 (2014.11); H04N 19/176 (2014.11)] 2 Claims
OG exemplary drawing
 
1. A decoder, comprising:
circuitry; and
memory, wherein
using the memory, the circuitry, in operation, determines to perform a decoding mode from among candidates including a decoder-side motion vector refinement (DMVR) decoding mode and a partition decoding mode,
when the DMVR decoding mode is determined to be performed, the circuitry:
obtains a first motion vector for a first image block;
derives a second motion vector from the first motion vector using motion search; and
generates a prediction image for the first image block using the second motion vector; and
when the partition decoding mode is determined to be performed, the circuitry:
determines a plurality of partitions in a second image block;
obtains a third motion vector for each partition; and
generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.