US 11,895,244 B2
Secure high-speed communication interface between a basic input and output system and a service processor
Wei G Liu, Austin, TX (US); and PoYu Cheng, Tainan (TW)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Jul. 27, 2021, as Appl. No. 17/385,972.
Prior Publication US 2023/0034670 A1, Feb. 2, 2023
Int. Cl. H04L 9/32 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/3242 (2013.01) [H04L 9/0825 (2013.01); H04L 9/3252 (2013.01); H04L 9/3297 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An information handling system, comprising:
a basic input/output system (BIOS) configured to:
generate, during a power-on self-test, a secret key that includes a symmetric key and a hash-based message authentication code key, wherein the secret key is stored in a system management interrupt handler;
transmit, during the power-on self-test, the secret key to a service processor via a high-speed communication interface; and
subsequent to the power-on self-test, transmit a system management interrupt message that includes an encrypted message and a first hash value of the encrypted message via the high-speed communication interface, wherein the encrypted message is encrypted using the symmetric key and the first hash value of the encrypted message is calculated using the hash-based message authentication code key of the secret key; and
the service processor configured to:
receive the system management interrupt message from the BIOS;
calculate a second hash value of encrypted message based on the hash-based message authentication code key;
verify the encrypted message by comparing the first hash value and the second hash value;
subsequent to a successful verification that the first hash value is equal to the second hash value, decrypt the encrypted message using the symmetric key; and
transmit a response to the BIOS via the high-speed communication interface.