US 11,895,218 B2
Ultra-low jitter low-power W/D-band phase-locked loop using power-gating injection-locked frequency multiplierbased phase detector
Jaehyouk Choi, Daejeon (KR); Suneui Park, Daejeon (KR); Seyeon Yoo, Daejeon (KR); Seojin Choi, Daejeon (KR); and Jooeun Bang, Daejeon (KR)
Assigned to KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon (KR)
Filed by Korea Advanced Institute of Science and Technology, Daejeon (KR)
Filed on Apr. 13, 2022, as Appl. No. 17/720,257.
Claims priority of application No. 10-2022-0004049 (KR), filed on Jan. 11, 2022.
Prior Publication US 2023/0224138 A1, Jul. 13, 2023
Int. Cl. H04L 7/033 (2006.01); H03L 7/08 (2006.01)
CPC H04L 7/033 (2013.01) [H03L 7/08 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A phase-locked loop comprising:
a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD),
wherein the PG-ILFM PD comprises:
a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF; and
a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO), wherein the R-VCO has a structure identical with a structure of the M-VCO and is used to multiply a frequency of the reference signal SREF.